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? semiconductor components industries, llc, 2008 september, 2008 ? rev. 1 1 publication order number: amis ? 30512/d amis-30512 micro-stepping motor driver introduction the amis ? 30512 is a micro ? stepping stepper motor driver for bipolar stepper motors. the chip is connected through i/o pins and a spi interface with an external microcontroller. it has an on ? chip voltage regulator, reset ? output and watchdog reset, able to supply peripheral devices. the amis ? 30512 contains a current ? translation table and takes the next micro ? step depending on the clock signal on the ?nxt? input pin and the status of the ?dir? (=direction) register or input pin. the chip provides a so ? called ?speed and load angle? output. this allows the creation of stall detection algorithms and control loops based on load ? angle to adjust torque and speed. it is using a proprietary pwm algorithm for reliable current control. the amis ? 30512 is implemented in i2t100 technology, enabling both high ? voltage analog circuitry and digital functionality on the same chip. the chip is fully compatible with the automotive voltage requirements. the amis ? 30512 is ideally suited for general ? purpose stepper motor applications in the automotive, industrial, medical, and marine environment. key features ? dual h ? bridge for 2 ? phase stepper motors ? programmable peak ? current up to 800 ma using a 5 ? bit current dac ? on ? chip current translator ? spi interface ? speed and load angle output ? seven step modes from full ? step up to 32 micro ? steps ? fully integrated current ? sense ? pwm current control with automatic selection of fast and slow decay ? low emc pwm with selectable voltage slopes ? active fly ? back diodes ? full output protection and diagnosis ? thermal warning and shutdown ? compatible with 3.3 v microcontrollers, 5 v tolerant inputs ? integrated 5 v regulator to supply external microcontroller ? integrated reset function to reset external microcontroller ? integrated watchdog function http://onsemi.com device package shipping ordering information AMIS30512 soic 24 tape & reel pin assignment (top view) tsto motxp vbb gnd motxn motyn gnd motyp vbb cs clr do di gnd clk nxt dir err sla cpn cpp vcp vdd AMIS30512 por /wd
amis ? 30512 http://onsemi.com 2 table of contents page introduction 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . key features 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ordering information 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . block diagram 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . pin list and descriptions 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . electrical specifications 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . typical application schematic 9 . . . . . . . . . . . . . . . . . . . . . . . functional description 10 . . . . . . . . . . . . . . . . . . . . . . . . . . . . spi interface 21 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . soldering information 29 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . package outline 30 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . figure 1. block diagram temp. sense spi otp timebase por di do clk nxt sla dir band ? gap load angle AMIS30512 logic & registers chargepump t r a n s l a t o r clr vbb p w m i ? sense emc p w m emc vdd gnd motxp motxn motyp motyn cpn cpp vcp tst0 err cs i ? sense vreg por /wd
amis ? 30512 http://onsemi.com 3 table 1. pin list and descriptions name pin description do 1 spi data output (open drain) vdd 2 logic supply input (needs external decoupling capacitor) gnd 3 ground di 4 spi data in clk 5 spi clock input nxt 6 next micro ? step input dir 7 direction input err 8 error output (open drain) sla 9 speed load angle output cpn 10 negative connection of charge pump capacitor cpp 11 positive connection of charge pump capacitor vcp 12 charge ? pump filter ? capacitor clr 13 ?clear? = chip reset input cs 14 spi chip select input vbb 15 high voltage supply input motyp 16 negative end of phase y coil output gnd 17 ground motyn 18 positive end of phase y coil output motxn 19 positive end of phase x coil output gnd 20 ground motxp 21 negative end of phase x coil output vbb 22 high voltage supply input por /wd 23 power ? on ? reset (por) and watchdog reset output (open drain) tst0 24 test pin input (to be tied to ground in normal operation) table 2. absolute maximum ratings symbol parameter min. max. units v bb analog dc supply voltage (note 1) ? 0.3 +40 v tstrg storage temperature ? 55 +160 c tamb ambient temperature under bias ? 50 +150 c v esd electrostatic discharges on component level (note 2) ? 2 +2 kv stresses exceeding maximum ratings may damage the device. maximum ratings are stress ratings only. functional operation above t he recommended operating conditions is not implied. extended exposure to stresses above the recommended operating conditions may af fect device reliability. 1. for limited time < 0.5 s. 2. human body model (100 pf via 1.5 k , according to jedec eia ? jesd22 ? a114 ? b). table 3. recommended operating conditions symbol parameter min. max. units v bb analog dc supply +6 +30 v t a ambient temperature v bb +18 ? 40 +125 c t a ambient temperature v bb +30 ? 40 +85 c t j junction temperature +160 c note: operating ranges define the limits for functional operation and parametric characteristics of the device. note that the fu nctionality of the chip outside these operating ranges is not guaranteed. operating outside the recommended operating ranges for extended periods of time may affect device reliability.
amis ? 30512 http://onsemi.com 4 table 4. dc parameters (the dc parameters are given for v bb and temperature in their operating ranges unless otherwise specified. convention: currents flowing in the circuit are defined as positive.) symbol pin(s) parameter remark/test conditions min. typ. max. unit supply inputs v bb vbb nominal operating supply range 6 30 v i bb total current consumption unloaded outputs 8 ma v dd vdd regulated output voltage 4.75 5 5.25 v i load max. output current 6 v < v bb < 8 v 20 ma 8 v < v bb < 30 v 50 ma i ddlim current limitation vdd shorted to ground 200 ma i load_pd output current in power down 1 ma power ? on ? reset (por) v ddh vdd internal por comparator threshold vdd rising 4.0 4.25 4.4 v v ddl internal por comparator threshold vdd falling 3.68 v motordriver i mdmax,peak motxp motxn motyp motyn max current through motor coil in normal operation tj < tstd 800 ma i mdabs absolute error on coil current ? 10 10 % i mdrel error on current ratio i coilx / i coily ? 7 7 % i set_tc temperature coefficient of coil current set ? level, cur[4:0] = 0 ..31 ? 40 c t j 160 c ? 240 ppm/ c r hs on ? resistance high ? side driver, cur[4:0] = 0...31; range 0...3 v bb = 12 v, t j = 27 c 0.45 0.56 v bb = 12 v, t j = 160 c 0.94 1.25 r ls3 on ? resistance low ? side driver, cur[4:0] = 23...31; range 3 v bb = 12 v, t j = 27 c 0.45 0.56 v bb = 12 v, t j = 160 c 0.94 1.25 r ls2 on ? resistance low ? side driver, cur[4:0] = 16...22; range 2 v bb = 12 v, t j = 27 c 0.90 1.2 v bb = 12 v, t j = 160 c 1.9 2.5 r ls1 on ? resistance low ? side driver, cur[4:0] = 9...15; range 1 v bb = 12 v, t j = 27 c 1.8 2.3 v bb = 12 v, t j = 160 c 3.8 5.0 r ls0 on ? resistance low ? side driver, cur[4:0] = 0...8; range 0 v bb = 12 v, t j = 27 c 3.6 4.5 v bb = 12 v, t j = 160 c 7.5 10 i mpd pull ? down current hiz mode 0.5 ma logic inputs i leak di, clk nxt, dir clr, csb input leakage (note 3) tj = 160 c 1 a v il logic low threshold 0 0.65 v v ih logic high threshold 2.20 v dd v r pd_clr clr internal pull ? down resistor 120 300 k r pd_tst tst0 internal pull ? down resistor 3 9 k 3. not valid for pins with internal pull ? down resistor 4. no more than 100 cumulated hours in life time above tt w 5. thermal shutdown and low temperature warning are derived from thermal warning.
amis ? 30512 http://onsemi.com 5 table 4. dc parameters (the dc parameters are given for v bb and temperature in their operating ranges unless otherwise specified. convention: currents flowing in the circuit are defined as positive.) symbol unit max. typ. min. remark/test conditions parameter pin(s) logical outputs v ol do, errb, por /wd logic low level open drain iol = 5 ma 0.5 v thermal warning and shutdown t tw thermal warning 138 145 152 c t tsd (notes 4,5) thermal shutdown t tw + 20 c charge pump v cp vcp output voltage 6 v < v bb < 15 v 2 * v bb ? 2.5 v 15 v < v bb < 30 v v bb +11 v bb +12.8 v bb +15 v c buffer external buffer capacitor 180 220 470 nf c pump cpp cpn external pump capacitor 180 220 470 nf speed and load angle output v out sla output voltage range 0.5 4.5 v v off output offset the sla pin 0.2 v < vsla < vdd ? 0,2 v -25 25 mv r out output resistance sla pin 1 k c load load capacitance sla pin 50 pf g sla gain of sla pin = v bemf / v coil slag=0 slag=1 0,5 0,25 3. not valid for pins with internal pull ? down resistor 4. no more than 100 cumulated hours in life time above tt w 5. thermal shutdown and low temperature warning are derived from thermal warning. table 5. ac parameters (the ac parameters are given for v bb and temperature in their operating ranges.) symbol pin(s) parameter remark/test conditions min. typ. max. unit internal oscillator f osc frequency of internal oscillator 3.6 4 4.4 mhz motordriver f pwm motxp motxn motyp motyn pwm frequency = 0 20.8 22.8 24.8 khz double pwm frequency = 1 41.6 45.6 49.6 khz f jf pwm jitter frequency not measured in production 50 hz f df pwm jitter depth 7 % f pwm t s_rise turn-on voltage slope, 10% to 90% i md = 800 ma emc[1:0] = 00 150 v/ s emc[1:0] = 01 100 v/ s emc[1:0] = 10 50 v/ s emc[1:0] = 11 25 v/ s t s_fall turn-off voltage slope, 90% to 10% i md = 800 ma emc[1:0] = 00 150 v/ s emc[1:0] = 01 100 v/ s emc[1:0] = 10 50 v/ s emc[1:0] = 11 25 v/ s t oc open coil detection time 200 ms
amis ? 30512 http://onsemi.com 6 table 5. ac parameters (the ac parameters are given for v bb and temperature in their operating ranges.) symbol unit max. typ. min. remark/test conditions parameter pin(s) digital outputs t h2l do errb output fall-time from v inh to v inl capacitive load 50 pf 50 ns charge pump f cp cpn cpp charge pump frequency 250 khz t cpu motxx start-up time of charge pump for typ. value c buffer and c pump 2 ms clr function t clr clr hard reset duration time 20 90 s nxt function t nxt_hi nxt nxt minimum, high pulse width see figure 2 2 s t nxt_lo nxt minimum, low pulse width see figure 2 2 s t dir_set nxt hold time, following change of dir see figure 2 0.5 s t dir_hold nxt hold time, before change of dir see figure 2 0.5 s power-up t pu por / wd power-up time v bb = 12 v, i load = 50 ma, c load = 220 nf. see figure 3 110 s t pd power-down time v bb = 12 v, i load = 50 ma, c load = 220 nf. . see figure 3 110 s t por reset duration see figure 3 100 ms t rf reset filter time see figure 3 1 s watchdog t wdto por / wd watchdog time out interval see figure 3 32 512 ms t wdpr prohibited watchdog acknowledge delay see figure 3 2 ms t wdrd watchdog reset delay 1 s figure 2. nxt ? input timing diagram ?? ?? ?? ?????????? ?????????? ?????????? dir nxt valid t dir_hold t dir_set t nxt_lo t nxt_hi 0,5 v cc
amis ? 30512 http://onsemi.com 7 figure 3. power ? on ? reset timing diagram t pu t por t rf vbb v ddh vdd v ddl t pd t wdpr and < t wdto t t t wdto
amis ? 30512 http://onsemi.com 8 table 6. spi timing parameters symbol parameter min. typ. max. unit t clk spi clock period 1 s t clk_high spi clock high time 100 ns t clk_low spi clock low time 100 ns t set_di di set up time, valid data before rising edge of clk 50 ns t hold_di di hold time, hold data after rising edge of clk 50 ns t csb_high csb high time 2.5 s t set_csb csb set up time, csb low before rising edge of clk 100 ns t set_clk clk set up time, clk low before rising edge of csb 100 ns figure 5. spi timing ?? ?? ?? ?????????? ?????????? ?????????? di valid clk 0,2 v cc 0,2 v cc 0,2 v cc 0,2 v cc cs 0,8 v cc t clk t set_clk t set_csb 0,8 v cc t clk_lo t clk_hi t hold_di t set_di
amis ? 30512 http://onsemi.com 9 figure 6. typical application schematic amis ? 30512 vcp cpp cpn clr c7 gnd clk di do nxt dir motxp motxn motyp motyn m 220 nf 100 nf c5 vdd vbb vbb 220 nf c2 c3 c6 c1 100 nf c4 sla c8 r1 d1 r2 r3 c v bat 100 f 100 nf 100 nf cs err por /wd r4 table 7. external components list and description component function typ. value tolerance unit c 1 v bb buffer capacitor (note 6) 100 ? 20 +80% f c 2 , c 3 v bb decoupling block capacitor 100 ? 20 +80% nf c 4 v dd buffer capacitor 220 20% nf c 5 v dd buffer capacitor 100 20% nf c 6 charge pump buffer capacitor 220 20% nf c 7 charge pump pumping capacitor 220 20% nf c 8 low pass filter sla 1 20% nf r 1 low pass filter sla 5.6 1% k r 2, r 3, r 4 pull up resistor 4.7 1% k d 1 optional reverse protection diode e.g. 1n4003 6. low esr < 1 ohm.
amis ? 30512 http://onsemi.com 10 functional description h ? bridge drivers a full h ? bridge is integrated for each of the two stator windings. each h ? bridge consists of two low ? side and two high ? side n ? type mosfet switches. writing logic ?0? in bit disables all drivers (high ? impedance). writing logic ?1? in this bit enables both bridges and current can flow in the motor stator windings. in order to avoid large currents through the h ? bridge switches, it is guaranteed that the top ? and bottom ? switches of the same half ? bridge are never conductive simultaneously (interlock delay). a two ? stage protection against shorts on motor lines is implemented. in a first stage, the current in the driver is limited. secondly, when excessive voltage is sensed across the transistor, the transistor is switched ? off. in order to reduce the radiated/conducted emission, voltage slope control is implemented in the output switches. the output slope is defined by the gate ? drain capacitance of output transistor and the (limited) current that drives the gate. there are two trimming bits for slope control (table 25: spi control parameter overview emc[1:0]). the power transistors are equipped with so ? called ?active diodes?: when a current is forced through the transistor switch in the reverse direction, i.e. from source to drain, then the transistor is switched on. this ensures that most of the current flows through the channel of the transistor instead of through the inherent parasitic drain ? bulk diode. depending on the desired current range and the micro ? step position at hand, the rdson of the low ? side transistors will be adapted such that excellent current ? sense accuracy is maintained. the rdson of the high ? side transistors remain unchanged, see table 4: dc parameters for more details. pwm current control a pwm comparator compares continuously the actual winding current with the requested current and feeds back the information to a digital regulation loop. this loop then generates a pwm signal, which turns on/off the h ? bridge switches. the switching points of the pwm duty ? cycle are synchronized to the on ? chip pwm clock. the frequency of the pwm controller can be doubled and an artificial jitter can be added (table 14 : spi control register 1). the pwm frequency will not vary with changes in the supply voltage. also variations in motor ? speed or load ? conditions of the motor have no effect. there are no external components required to adjust the pwm frequency. automatic forward and slow ? fast decay the pwm generation is in steady ? state using a combination of forward and slow ? decay. the absence of fast ? decay in this mode, guarantees the lowest possible current ? ripple ?by design?. for transients to lower current levels, fast ? decay is automatically activated to allow high ? speed response. the selection of fast or slow decay is completely transparent for the user and no additional parameters are required for operation. figure 7. forward and slow/fast decay pwm icoil 0 t forward & slow decay actual value set value fast decay & forward t pwm forward & slow decay in case the supply voltage is lower than 2*bemf, then the duty cycle of the pwm is adapted automatically to >50% to maintain the requested average current in the coils. this process is completely automatic and requires no additional parameters for operation. the over ? all current ? ripple is divided by two if pwm frequency is doubled (table 14: spi control register 1).
amis ? 30512 http://onsemi.com 11 figure 8. automatic duty cycle adaptation actual value duty cycle < 50% duty cycle > 50% duty cycle < 50% t icoil set value t pwm step translator step mode the step translator provides the control of the motor by means of spi register stepmode: sm[2:0], spi register dircntrl, and input pins dir and nxt. it is translating consecutive steps in corresponding currents in both motor coils for a given step mode. one out of seven possible stepping modes can be selected through spi ? bits sm[2:0] (table 26: spi control parameter overview sm[2:0]) after power ? on or hard reset, the coil ? current translator is set to the default 1/32 micro ? stepping at position ?0?. upon changing the step mode, the translator jumps to position 0* of the corresponding stepping mode. when remaining in the same step mode, subsequent translator positions are all in the same column and increased or decreased with 1. table 9 lists the output current versus the translator position. as shown in figure 9 the output current ? pairs can be projected approximately on a circle in the (i x ,i y ) plane. there is, however, one exception: uncompensated half step. in this step mode the currents are not regulated to a fraction of imax but are in all intermediate steps regulated at 100 percent. in the (i x ,i y ) plane the current ? pairs are projected on a square. table 8 lists the output current versus the translator position for this case. table 8. square translator table for full step and uncompensated half step msp[6:0] stepmode ( sm[2:0] ) % of imax 101 110 coil x coil y uncompensated half ? step full step 000 0000 0* ? 0 100 001 0000 1 1 100 100 010 0000 2 ? 100 0 011 0000 3 2 100 ? 100 100 0000 4 ? 0 ? 100 101 0000 5 3 ? 100 ? 100 110 0000 6 ? ? 100 0 111 0000 7 0* ? 100 100
amis ? 30512 http://onsemi.com 12 table 9. circular translator table msp[6:0] stepmode ( sm[2:0] ) % of imax 000 001 010 011 100 coil x coil y 1/32 1/16 1/8 1/4 1/2 000 0000 ?0? 0* 0* 0* 0* 0 100 000 0001 1 - - - - 3.5 98.8 000 0010 2 1 - - - 8.1 97.7 000 0011 3 - - - - 12.7 96.5 000 0100 4 2 1 - - 17.4 95.3 000 0101 5 - - - - 22.1 94.1 000 0110 6 3 - - - 26.7 93 000 0111 7 - - - - 31.4 91.8 000 1000 8 4 2 1 - 34.9 89.5 000 1001 9 - - - - 38.3 87.2 000 1010 10 5 - - - 43 84.9 000 1011 11 - - - - 46.5 82.6 000 1100 12 6 3 - - 50 79 000 1101 13 - - - - 54.6 75.5 000 1110 14 7 - - - 58.1 72.1 000 1111 15 - - - - 61.6 68.6 001 0000 16 8 4 2 1 65.1 65.1 001 0001 17 - - - - 68.6 61.6 001 0010 18 9 - - - 72.1 58.1 001 0011 19 - - - - 75.5 54.6 001 0100 20 10 5 - - 79 50 001 0101 21 - - - - 82.6 46.5 001 0110 22 11 - - - 84.9 43 001 0111 23 - - - - 87.2 38.3 001 1000 24 12 6 3 - 89.5 34.9 001 1001 25 - - - - 91.8 31.4 001 1010 26 13 - - - 93 26.7 001 1011 27 - - - - 94.1 22.1 001 1100 28 14 7 - - 95.3 17.4 001 1101 29 - - - - 96.5 12.7 001 1110 30 15 - - - 97.7 8.1 001 1111 31 - - - - 98.8 3.5 010 0000 32 16 8 4 2 100 0 010 0001 33 - - - - 98.8 -3.5 010 0010 34 17 - - - 97.7 -8.1 010 0011 35 - - - - 96.5 -12.7 010 0100 36 18 9 - - 95.3 -17.4 010 0101 37 - - - - 94.1 -22.1 010 0110 38 19 - - - 93 -26.7 010 0111 39 - - - - 91.8 -31.4 010 1000 40 20 10 5 - 89.5 -34.9 010 1001 41 - - - - 87.2 -38.3 010 1010 42 21 - - - 84.9 -43
amis ? 30512 http://onsemi.com 13 table 9. circular translator table msp[6:0] % of imax stepmode ( sm[2:0] ) msp[6:0] coil y coil x 100 011 010 001 000 msp[6:0] coil y coil x 1/2 1/4 1/8 1/16 1/32 010 1011 43 - - - - 82.6 -46.5 010 1100 44 22 11 - - 79 -50 010 1101 45 - - - - 75.5 -54.6 010 1110 46 23 - - - 72.1 -58.1 010 1111 47 - - - - 68.6 -61.6 011 0000 48 24 12 6 3 65.1 -65.1 011 0001 49 - - - - 61.6 -68.6 011 0010 50 25 - - - 58.1 -72.1 011 0011 51 - - - - 54.6 -75.5 011 0100 52 26 13 - - 50 -79 011 0101 53 - - - - 46.5 -82.6 011 0110 54 27 - - - 43 -84.9 011 0111 55 - - - - 38.3 -87.2 011 1000 56 28 14 7 - 34.9 -89.5 011 1001 57 - - - - 31.4 -91.8 011 1010 58 29 - - - 26.7 -93 011 1011 59 - - - - 22.1 -94.1 011 1100 60 30 15 - - 17.4 -95.3 011 1101 61 - - - - 12.7 -96.5 011 1110 62 31 - - - 8.1 -97.7 011 1111 63 - - - - 3.5 -98.8 100 0000 64 32 16 8 4 0 -100 100 0001 65 - - - - -3.5 -98.8 100 0010 66 33 - - - -8.1 -97.7 100 0011 67 - - - - -12.7 -96.5 100 0100 68 34 17 - - -17.4 -95.3 100 0101 69 - - - - -22.1 -94.1 100 0110 70 35 - - - -26.7 -93 100 0111 71 - - - - -31.4 -91.8 100 1000 72 36 18 9 - -34.9 -89.5 100 1001 73 - - - - -38.3 -87.2 100 1010 74 37 - - - -43 -84.9 100 1011 75 - - - - -46.5 -82.6 100 1100 76 38 19 - - -50 -79 100 1101 77 - - - - -54.6 -75.5 100 1110 78 39 - - - -58.1 -72.1 100 1111 79 - - - - -61.6 -68.6 101 0000 80 40 20 10 5 -65.1 -65.1 101 0001 81 - - - - -68.6 -61.6 101 0010 82 41 - - - -72.1 -58.1 101 0011 83 - - - - -75.5 -54.6 101 0100 84 42 21 - - -79 -50 101 0101 85 - - - - -82.6 -46.5
amis ? 30512 http://onsemi.com 14 table 9. circular translator table msp[6:0] % of imax stepmode ( sm[2:0] ) msp[6:0] coil y coil x 100 011 010 001 000 msp[6:0] coil y coil x 1/2 1/4 1/8 1/16 1/32 101 0110 86 43 - - - -84.9 -43 101 0111 87 - - - - -87.2 -38.3 101 1000 88 44 22 11 - -89.5 -34.9 101 1001 89 - - - - -91.8 -31.4 101 1010 90 45 - - - -93 -26.7 101 1011 91 - - - - -94.1 -22.1 101 1100 92 46 23 - - -95.3 -17.4 101 1101 93 - - - - -96.5 -12.7 101 1110 94 47 - - - -97.7 -8.1 101 1111 95 - - - - -98.8 -3.5 110 0000 96 48 24 12 6 -100 0 110 0001 97 - - - - -98.8 3.5 110 0010 98 49 - - - -97.7 8.1 110 0011 99 - - - - -96.5 12.7 110 0100 100 50 25 - - -95.3 17.4 110 0101 101 - - - - -94.1 22.1 110 0110 102 51 - - - -93 26.7 110 0111 103 - - - - -91.8 31.4 110 1000 104 52 26 13 - -89.5 34.9 110 1001 105 - - - - -87.2 38.3 110 1010 106 53 - - - -84.9 43 110 1011 107 - - - - -82.6 46.5 110 1100 108 54 27 - - -79 50 110 1101 109 - - - - -75.5 54.6 110 1110 110 55 - - - -72.1 58.1 110 1111 111 - - - - -68.6 61.6 111 0000 112 56 28 14 7 -65.1 65.1 111 0001 113 - - - - -61.6 68.6 111 0010 114 57 - - - -58.1 72.1 111 0011 115 - - - - -54.6 75.5 111 0100 116 58 29 - - -50 79 111 0101 117 - - - - -46.5 82.6 111 0110 118 59 - - - -43 84.9 111 0111 119 - - - - -38.3 87.2 111 1000 120 60 30 15 - -34.9 89.5 111 1001 121 - - - - -31.4 91.8 111 1010 122 61 - - - -26.7 93 111 1011 123 - - - - -22.1 94.1 111 1100 124 62 31 - - -17.4 95.3 111 1101 125 - - - - -12.7 96.5 111 1110 126 63 - - - -8.1 97.7 111 1111 127 - - - - -3.5 98.8
amis ? 30512 http://onsemi.com 15 figure 9. translator table: circular and square uncompensated half step full step start = 0 step 1 step 2 step 3 i x 1/4 th micro step i y start = 0 i y step 1 step 2 i x step 3 sm[2:0] = 011 sm[2:0] = 101 i y start = 0 step 1 sm[2:0] = 110 step 3 i x step 2 direction the direction of rotation is selected by means of following combination of the dir input pin and the spi ? controlled direction bit . (table 14: spi control register 1) nxt input changes on the nxt input will move the motor current one step up/down in the translator table. depending on the nxt ? polarity bit (table 14: spi control register 1), the next step is initiated either on the rising edge or the falling edge of the nxt input. translator position the translator position can be read in table 30: spi status register 3. this is a 7 ? bit number equivalent to the 1/32th micro ? step from table 9: circular translator table. the translator position is updated immediately following a nxt trigger. figure 10. translator position timing diagram nxt update translator position update translator position synchronization of step mode and nxt input when step mode is re ? programmed to another resolution (table 13: spi control register 0), then this is put in effect immediately upon the first arriving ?nxt? input. if the micro ? stepping resolution is increased (see figure 11 left hand side) then the coil currents will be regulated to the nearest micro ? step, according to the fixed grid of the increased resolution. if however the micro ? stepping resolution is decreased, then it is possible to introduce an offset (or phase shift) in the micro ? step translator table. if the step resolution is decreased at a translator table position that is shared both by the old and new resolution setting, then the offset is zero and micro ? stepping proceeds according to the translator table. if the step resolution is decreased at a translator table position that is shared both by the old and new resolution setting, then the offset is zero and micro-stepping is proceeds according to the translator table. if the translator position is not shared both by the old and new resolution setting, then the micro ? stepping proceeds with an offset relative to the translator table (see figure 11 right hand side).
amis ? 30512 http://onsemi.com 16 figure 11. nxt ? step mode synchronization ix dir iy ix iy dir nxt1 nxt2 nxt3 nxt4 halfstep endpos change from lower to higher resolution startpos iy ix iy ix dir nxt1 nxt2 nxt3 dir endpos halfstep change from higher to lower resolution startpos left: change from lower to higher resolution. the left ? hand side depicts the ending half ? step position during which a new step mode resolution was programmed. the right ? hand side diagram shows the effect of subsequent nxt commands on the micro ? step position. right: change from higher to lower resolution. the left ? hand side depicts the ending micro ? step position during which a new step mode resolution was programmed. the right ? hand side diagram shows the effect of subsequent nxt commands on the half ? step position. 1/4 th step 1/8 th step note: it is advised to reduce the micro ? stepping resolution only at micro ? step positions that overlap with desired micro ? step positions of the new resolution. programmable peak ? current the amplitude of the current waveform in the motor coils (coil peak current = imax) is adjusted by means of an spi parameter ?cur[4:0]? (table 13: spi control register 0). whenever this parameter is changed, the coil ? currents will be updated immediately at the next pwm period. the impedance of the bottom drivers is adapted with the current range: see table 4: dc parameters. table 10. programmable peak current cur[4:0] current range cur[4:0] index current (ma) current range cur[4:0] index current (ma) 0 0 15 2 16 181 1 30 17 200 2 45 18 221 3 50 19 244 4 55 20 269 5 61 21 297 6 67 22 328 7 74 3 23 362 8 82 24 400 1 9 91 25 441 10 100 26 487 11 110 27 538 12 122 28 594 13 135 29 656 14 149 30 724 15 164 31 800 note: changing the current over different current ranges might lead to false over current triggering.
amis ? 30512 http://onsemi.com 17 speed and load angle output the sla ? pin provides an output voltage that indicates the level of the back ? e.m.f. voltage of the motor. this back ? e.m.f. voltage is sampled during every so ? called ?coil current zero crossings?. per coil, two zero ? current positions exist per electrical period, yielding in total four zero ? current observation points per electrical period. figure 12. principle of bemf measurement v bemf zoom t voltage transient next micro ? step coil current zero crossing current decay zero current t t i coil previous micro ? step i coil v coil v bb v bemf because of the relatively high recirculation currents in the coil during current decay, the coil voltage v coil shows a transient behavior. as this transient is not always desired in application software, two operating modes can be selected by means of the bit (see ?sla ? transparency? in table 15: spi control register 2). the sla pin shows in ?transparent mode? full visibility of the voltage transient behavior. this allows a sanity ? check of the speed ? setting versus motor operation and characteristics and supply voltage levels. if the bit ?slat? is cleared, then only the voltage samples at the end of each coil current zero crossing are visible on the sla ? pin. because the transient behavior of the coil voltage is not visible any more, this mode generates smoother back e.m.f. input for post ? processing, e.g. by software. in order to bring the sampled back e.m.f. to a descent output level (0 to 5 v), the sampled coil voltage v coil is divided by 2 or by 4. this divider is set through an spi bit . (table 15: spi control register 2) the following drawing illustrates the operation of the sla ? pin and the transparency ? bit. ?pwmsh? and ?icoil=0? are internal signals that define together with slat the sampling and hold moments of the coil voltage.
amis ? 30512 http://onsemi.com 18 figure 13. timing diagram of sla ? pin pwmsh icoil = 0 slat sla ? pin last sample is retained retain last sample previous output is kept at sla pin buf ssh sh ch csh slat not (icoil = 0) icoil = 0 pwmsh sla ? pin div2 div4 t t slat = 0 sla ? pin is not ?transparent? during v bemf sampling @ coil current zero crossing. sla ? pin is updated when leaving current ? less state. slat = 1 sla ? pin is ?transparent? during v bemf sampling @ coil current zero crossing. sla ? pin is updated ?real ? time?. v bemf v coil v coil warning, error detection and diagnostics feedback thermal warning and shutdown when junction temperature rises above t tw , the thermal warning bit is set (table 27: spi status register 0). if junction temperature increases above thermal shutdown level, then the circuit goes in ?thermal shutdown? mode, bit is set and all driver transistors are disabled (high impedance) (table 29: spi status register 2). the conditions to reset flag is to be at a temperature lower than t tw and to clear the flag by reading it using any spi read command. over ? current detection the over ? current detection circuit monitors the load current in each activated output stage. if the load current exceeds the over ? current detection threshold, then the over ? current flag is set and the drivers are switched off to reduce the power dissipation and to protect the integrated circuit. each driver transistor has an individual detection bit in the table 28: spi status register 1 and table 29: spi status register 2 ( and ). error condition is latched and the microcontroller needs to clean the status bits to reactivate the drivers. note: successive reading the spi status registers 1 and 2 in case of a short circuit condition, may lead to damage to the drivers. changing the current over different current ranges might lead to false over current triggering. open coil detection open coil detection is based on the observation of 100 percent duty cycle of the pwm regulator. if in a coil 100 percent duty cycle is detected for longer than t oc = 200 ms then the related driver transistors are disabled (high ? impedance) and an appropriate bit in the spi status register is set ( or ). (table 27: spi status register 0). charge pump failure the charge pump is an important circuit that guarantees low rdson for all drivers, especially for low supply voltages. if the supply voltage is too low or external components are
amis ? 30512 http://onsemi.com 19 not properly connected to guarantee sufficient low rdson of the drivers, then the bit is set in table 27: spi status register 0. also after power ? on ? reset the charge pump voltage will need the time t cpu to exceed the required threshold. during that time will be set to ?1?. error output this is a digital output to flag a problem to the external microcontroller. the signal on this output is active low and the logic combination of: not(errb) = or or or or or logic supply regulator amis-30512 has an on-chip 5 v low-drop regulator with external decoupling capacitor to supply the digital part of the chip, some low-voltage analog blocks and external circuitry. the voltage is derived from an internal bandgap reference. to calculate the available drive-current for external circuitry, the specified i load should be reduced with the consumption of internal circuitry (unloaded outputs) and the loads connected to logic outputs. see dc parameters. power-on reset (por) function the open drain output pin por /wd provides an ?active low? reset for external purposes. at power-up of amis-30512, this pin will be kept low for some time to reset for example an external microcontroller. a small analog filter avoids resetting due to spikes or noise on the vdd supply. vbb vdd t t figure 14. power ? on ? reset timing diagram v ddh v ddl t pu t pd por /wd pin < t rf t por t rf watchdog function the watchdog function is enabled/disabled through bit (table 12: spi control register wr). once this bit has been set to ?1? (watchdog enable), the microcontroller needs to re-write this bit to clear an internal timer before the watchdog timeout interval expires. in case the timer is activated and wden is acknowledged too early (before t wdpr ) or not within the interval (after t wdto ), then a reset of the microcontroller will occur through por /wd pin. in addition, a warm/cold boot bit is available in spi status register 0 for further processing when the external microcontroller is alive again. the watchdog reset delay t wdrd is determined by an internal delay of 0,5 s added to an external delay formed by the pull up resistance and the capacitive load on the por /wd pin.
amis ? 30512 http://onsemi.com 20 vbb vdd t t enable wd acknowledge wd wd timer t t figure 15. watchdog timing diagram t wdto v ddh t pu t dspi t por por /wd pin t por t wdrd = t wdpr or = t wdto > t wdpr or < t wdto note: t dspi is the time needed by the external microcontroller to shift-in the bit after a power-up. the duration of the watchdog timeout interval is programmable through the wdt [3:0] bits (table 12: spi control register wr). the timing is given in table 11. table 11. watchdog timeout interval as function of wdt[3.0] index wdt[3:0] t wdto (ms) 0 0 0 0 0 32 1 0 0 0 1 64 2 0 0 1 0 96 3 0 0 1 1 128 4 0 1 0 0 160 5 0 1 0 1 192 6 0 1 1 0 224 7 0 1 1 1 256 8 1 0 0 0 288 9 1 0 0 1 320 a 1 0 1 0 352 b 1 0 1 1 384 c 1 1 0 0 416 d 1 1 0 1 448 e 1 1 1 0 480 f 1 1 1 1 512 clr pin (=hard reset) logic 0 on clr pin allows normal operation of the chip. to reset the complete digital inside amis ? 30512, the input clr needs to be pulled to logic 1 during minimum time given by t clr . (table 5: ac parameters) this reset function clears all internal registers without the need of a power ? cycle. the operation of all analog circuits is depending on the reset state of the digital, charge pump remains active. logic 0 on clr pin resumes normal operation again. sleep mode the bit in table 15: spi control register 2 is provided to enter a so ? called ?sleep mode?. this mode allows reduction of current ? consumption when the motor is not in operation. the effect of sleep mode is as follows: ? the drivers are put in hiz ? all analog circuits are disabled and in low ? power mode ? all internal registers are maintaining their logic content ? pulses on nxt and dir inputs are ignored ? spi communication remains possible (slight current increase during spi communication) ? reset of chip is possible through clr pin ? oscillator and digital clocks are silent, except during spi communication normal operation is resumed after writing logic ?0? to bit . a start ? up time t cpu is needed for the charge pump to stabilize. after this time, nxt commands can be issued.
amis ? 30512 http://onsemi.com 21 spi interface the serial peripheral interface (spi) allows an external microcontroller (master) to communicate with amis ? 30512. the implemented spi block is designed to interface directly with numerous micro ? controllers from several manufacturers. amis ? 30512 acts always as a slave and can?t initiate any transmission. the operation of the device is configured and controlled by means of spi registers which are observable for read and/or write from the master. spi transfer format and pin signals during a spi transfer, data is simultaneously transmitted (shifted out serially) and received (shifted in serially). a serial clock line (clk) synchronizes shifting and sampling of the information on the two serial data lines (do and di). do signal is the output from the slave (amis ? 30512), and di signal is the output from the master. a chip select line (csb) allows individual selection of a slave spi device in a multiple ? slave system. the csb line is active low. if amis ? 30512 is not selected, do is pulled up with the external pull up resistor. since amis ? 30512 operates as a slave in mode 0 (cpol = 0; cpha = 0) it always clocks data out on the falling edge and samples data in on rising edge of clock. the master spi port must be configured in mode 0 too, to match this operation. the spi clock idles low between the transferred bytes. the diagram below is both a master and a slave timing diagram since clk, do and di pins are directly connected between the master and the slave. figure 16. timing diagram of a spi transfer ???? ???? ????? ????? di msb clk 1 2 3 4 5 6 7 8 do # clk cycle msb lsb lsb 6 543 21 6 543 21 cs note: at the falling edge of the eight clock pulse the data ? out shift register is updated with the content of the addressed internal spi register. the internal spi registers are updated at the first rising edge of the amis ? 30512 system clock when csb = high transfer packet: serial data transfer is assumed to follow msb first rule. the transfer packet contains one or more bytes. figure 17. spi transfer packet command and spi register address data byte 2 byte 1 d7 d6 d5 d4 d3 d2 d1 d0 lsb msb command spi register address lsb msb cmd2 cmd1 cmd0 addr4 addr3 addr2 addr1 addr0
amis ? 30512 http://onsemi.com 22 byte 1 contains the command and the spi register address and indicates to amis ? 30512 the chosen type of operation and addressed register. byte 2 contains data, or sent from the master in a write operation, or received from amis ? 30512 in a read operation. 2 command types can be distinguished in the communication between master and amis ? 30512: ? read from spi register with address addr[4:0]: cmd2 = ?0? ? write to spi register with address addr[4:0]: cmd2 = ?1? read operation if the master wants to read data from status or control registers, it initiates the communication by sending a read command. this read command contains the address of the spi register to be read out. at the falling edge of the eight clock pulse the data ? out shift register is updated with the content of the corresponding internal spi register. in the next 8 ? bit clock pulse train this data is shifted out via do pin. at the same time the data shifted in from di (master) should be interpreted as the following successive command or is dummy data. figure 18. single read operation where data from spi register with address 1 is read by the master di do read data from addr1 command or dummy data from addr1 old data or not valid command data data data from previous command or not valid after por or reset cs registers are updated with the internal status at the rising edge of the internal amis ? 30512 clock when cs = 1 all 4 status registers (see spi status registers) contain 7 data bits and a parity check bit. the most significant bit (d7) represents a parity of d[6:0]. if the number of logical ones in d[6:0] is odd, the parity bit d7 equals ?1?. if the number of logical ones in d[6:0] is even then the parity bit d7 equals ?0?. this simple mechanism protects against noise and increases the consistency of the transmitted data. if a parity check error occurs it is recommended to initiate an additional read command to obtain the status again. also the control registers (see spi control registers) can be read out following the same routine. control registers don?t have a parity check. the csb line is active low and may remain low between successive read commands as illustrated in figure 18. there is however one exception. in case an error condition is latched in one of status registers (see spi registers) the errb pin is activated. (see error output). this signal flags a problem to the external microcontroller. by reading the status registers information about the root cause of the problem can be determined. after this read operation the status registers are cleared. because the status registers and errb pin are only updated by the internal system clock when the csb line is high, the master should force csb high immediately after the read operation. for the same reason it is recommended to keep the csb line high always when the spi bus is idle. write operation if the master wants to write data to a control register it initiates the communication by sending a write command. this contains the address of the spi register to write to. the command is followed with a data byte. this incoming data will be stored in the corresponding control register after csb goes from low to high! amis ? 30512 responds on every incoming byte by shifting out via do the data stored in the last received address. it is important that the writing action (command ? address and data) to the control register is exactly 16 bits long. if more or less bits are transmitted the complete transfer packet is ignored. a write command executed for a read ? only register (e.g. status registers) will not affect the addressed register and the device operation. because after a power ? on ? reset the initial address is unknown the data shifted out via do is not valid.
amis ? 30512 http://onsemi.com 23 figure 19. single write operation where data from the master is written in spi register with address 3 di do write data to addr3 new data for addr3 old data from addr3 old data or not valid command data data data from previous command or not valid after por or reset data cs the new data is written into the corresponding internal register at the rising edge of cs examples of combined read and write operations in the following examples successive read and write operations are combined. in figure 17 the master first reads the status from register at addr4 and at addr5 followed by writing a control byte in control register at addr2. note that during the write command (in figure 3) the old data of the pointed register is returned at the moment the new data is shifted in: figure 20. 2 successive read commands followed by a write command di do read from addr4 data old data command data data data from previous command or not valid after por or reset command command data data data read from addr5 write data to addr2 the new data is written into the corresponding internal register at the rising edge of cs registers are updated with the internal status at the rising edge of the internal amis ? 30512 clock when cs = 1 cs or not valid from addr4 data from addr5 old data from addr2 new data for addr2 data data after the write operation the master could initiate a read back command in order to verify the data correctly written as illustrated in figure 18. during reception of the read command the old data is returned for a second time. only after receiving the read command the new data is transmitted. this rule also applies when the master device wants to initiate an spi transfer to read the status registers. because the internal system clock updates the status registers only when csb line is high, the first read out byte might represent old status information. figure 21. a write operation where data from the master is written in spi register with address 2 followed by a read back operation to confirm a correct write operation di do write to addr2 old data command data data command data data new for addr2 read from addr2 command data old data new data registers are updated with the internal status at the rising edge of the internal amis ? 30512 clock when cs = 1 registers are updated with the internal status at the rising edge of cs from addr2 old data from addr2 or not valid from addr2 cs or dummy data data data data from previous com- mand or not valid after por or reset note: the internal data ? out shift buffer of amis ? 30512 is updated with the content of the selected spi register only at the last (every eight) falling edge of the clk signal (see spi transfer format and pin signals). as a result, new data for transmission cannot be written to the shift buffer at the beginning of the transfer packet and the first byte shifted out might represent old data.
amis ? 30512 http://onsemi.com 24 spi control registers all spi control registers have read/write access and default to ?0? after power ? on or hard reset. table 12. spi control register wr control register (wr) address content structure bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 00h access r/w r/w r/w r/w r/w r/w r/w r/w reset 0 0 0 0 0 0 0 0 data wden wdt[3:0] ? ? ? where : r/w read and write access reset: status after power-on or hard reset wden: watchdog enable. writing ?1? to this bit will activate the watchdog timer (if not enabled yet) or will clear this timer (if already enabled). writing ?0? to this bit will clear wd bit (spi status register 0). wdt[3:0]: watchdog timeout interval table 13. spi control register 0 control register 0 (cr0) address content structure bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 01h access r/w r/w r/w r/w r/w r/w r/w r/w reset 0 0 0 0 0 0 0 0 data sm[2:0] cur[4:0] where : r/w read and write access reset: status after power ? on or hard reset sm[2:0] : step mode cur[4:0] : current amplitude table 14. spi control register 1 control register 1 (cr1) address content structure bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 02h access r/w r/w r/w r/w r/w r/w r/w r/w reset 0 0 0 0 0 0 0 0 data dirctrl nxtp ? ? pwmf pwmj emc[1:0] where : r/w read and write access reset: status after power ? on or hard reset dirctrl direction control nxtp next polarity pwmf pwm frequency pwmj pwm jitter emc[1:0] emc slope control
amis ? 30512 http://onsemi.com 25 table 15. spi control register 2 control register 2 (cr2) address content structure bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 03h access r/w r/w r/w r/w r/w r/w r/w r/w reset 0 0 0 0 0 0 0 0 data moten slp slag slat ? ? ? ? where : r/w read and write access reset: status after power ? on or hard reset moten motor enable slp sleep slag speed load angle gain slat speed load angle transparency table 16. spi control parameter overview slat symbol description status behaviour slat speed load angle transparency bit = 0 sla is transparent = 1 sla is not transparent table 17. spi control parameter overview slag symbol description status value slag speed load angle gain setting = 0 gain = 0.5 = 1 gain = 0.25 table 18. spi control parameter overview pwmf symbol description status value pwmf enables doubling of the pwm frequency = 0 f pwm = 22.8 khz = 1 f pwm = 45.6 khz table 19. spi control parameter overview pwmj symbol description status behaviour pwmj enables jittery pwm = 0 jitter disabled = 1 jitter enabled table 20. spi control parameter overview slp symbol description status behaviour slp enables sleep mode = 0 active mode = 1 sleep mode table 21. spi control parameter overview moten symbol description status value moten activates the motor driver outputs = 0 drivers disabled = 1 drivers enabled table 22. spi control parameter overview dirctrl symbol description status value dirctrl controls the direction of rotation (in combination with logic level on input dir) = 0 = 0 cw motion = 1 ccw motion = 1 = 0 ccw motion = 1 cw motion table 23. spi control parameter overview nxtp symbol description status value nxtp selects if nxt triggers on rising or falling edge = 0 trigger on rising edge = 1 trigger on falling edge cur[4:0] selects imcmax peak. this is the peak or amplitude of the regulated current waveform in the motor coils.
amis ? 30512 http://onsemi.com 26 table 24. spi control parameter overview cur[4:0] index cur[4:0] current (ma) index cur[4:0] current (ma) 0 0 0 0 0 0 15 10 1 0 0 0 0 181 1 0 0 0 0 1 30 11 1 0 0 0 1 200 2 0 0 0 1 0 45 12 1 0 0 1 0 221 3 0 0 0 1 1 50 13 1 0 0 1 1 244 4 0 0 1 0 0 55 14 1 0 1 0 0 269 5 0 0 1 0 1 61 15 1 0 1 0 1 297 6 0 0 1 1 0 67 16 1 0 1 1 0 328 7 0 0 1 1 1 74 17 1 0 1 1 1 362 8 0 1 0 0 0 82 18 1 1 0 0 0 400 9 0 1 0 0 1 91 19 1 1 0 0 1 441 a 0 1 0 1 0 100 1a 1 1 0 1 0 487 b 0 1 0 1 1 110 1b 1 1 0 1 1 538 c 0 1 1 0 0 122 1c 1 1 1 0 0 594 d 0 1 1 0 1 135 1d 1 1 1 0 1 656 e 0 1 1 1 0 149 1e 1 1 1 1 0 724 f 0 1 1 1 1 164 1f 1 1 1 1 1 800 emc[1:0] adjusts the dv/dt of the pwm voltage slopes on the motor pins. table 25. spi control parameter overview emc[1:0] index emc[1:0] slope (v/ s) remark 0 0 0 150 turn ? on and turn ? off voltage slope 10% to 90% 1 0 1 100 ? 2 1 0 50 ? 3 1 1 25 ? sm[2:0] selects the micro ? stepping mode. table 26. spi control parameter overview sm[2:0] index sm[2:0] step mode remark 0 0 0 0 1/32 micro ? step 1 0 0 1 1/16 micro ? step 2 0 1 0 1/8 micro ? step 3 0 1 1 1/4 micro ? step 4 1 0 0 1/2 uncompensated half ? step 5 1 0 1 1/2 compensated half ? step 6 1 1 0 full full step 7 1 1 1 n/a for future use
amis ? 30512 http://onsemi.com 27 spi status register description all four spi status registers have read access and are default to ?0? after power ? on or hard reset. table 27. status register 0 (sr0) address content structure bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 04h access r r r r r r r r reset 0 0 0 0 0 0 0 0 data par tw cpfail ? openx openy ? ? where : r read only mode access reset status after power ? on or hard reset par parity check tw thermal warning cpfail charge pump failure openx open coil x detected openy open coil y detected remark : data is not latched table 28. status register 1 (sr1) address content structure bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 05h access r r r r r r r r reset 0 0 0 0 0 0 0 0 data par ovcxpt ovcxpb ovcxnt ovcxnb ? ? ? where : r read only mode access reset status after power ? on or hard reset par parity check ovxpt over ? current detected on x h ? bridge: motxp terminal, top transistor ovxpb over ? current detected on x h ? bridge: motxp terminal, bottom transistor ovxnt over ? current detected on x h ? bridge: motxn terminal, top transistor ovxnb over ? current detected on x h ? bridge: motxn terminal, bottom transistor remark : data is latched table 29. spi status register 2 (sr2) address content structure bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 06h access r r r r r r r r reset 0 0 0 0 0 0 0 0 data par ovcypt ovcypb ovcyynt ovcynb tsd ? ? where : r read only mode access reset status after power ? on or hard reset par parity check ovcypt over ? current detected on y h ? bridge: motyp terminal, top transistor ovcypb over ? current detected on y h ? bridge: motyp terminal, bottom transistor ovcynt over ? current detected on y h ? bridge: motyn terminal, top transistor ovcynb over ? current detected on y h ? bridge: motyn terminal, bottom transistor tsd thermal shutdown remark : data is latched
amis ? 30512 http://onsemi.com 28 table 30. spi status register 3 (sr3) address content structure bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 07h access r r r r r r r r reset 0 0 0 0 0 0 0 0 data par msp[6:0] where : r read only mode access reset status after power ? on or hard reset par parity check msp[6:0] translator micro ? step position remark : data is not latched table 31. spi status flags overview flag mnemonic length (bit) related spi register comment reset state charge pump failure cpfail 1 status register 0 ?0? = no failure ?1? = failure: indicates that the charge pump does not reach the required voltage level. ?0? micro ? step position msp [6:0] 7 status register 3 translator micro ? step position ?0000000? open coil x openx 1 status register 0 ?1? = open coil detected ?0? open coil y openy 1 status register 0 ?1? = open coil detected ?0? over current on x h ? bridge; motxn terminal; bottom tran. ovcxnb 1 status register 1 ?0? = no failure ?1? = failure: indicates that over current is detected at bottom transistor xn ? terminal ?0? over current on x h ? bridge; motxn terminal; top tran. ovcxnt 1 status register 1 ?0? = no failure ?1? = failure: indicates that over current is detected at top transistor xn ? terminal ?0? over current on x h ? bridge; motxp terminal; bottom tran. ovcxpb 1 status register 1 ?0? = no failure ?1? = failure: indicates that over current is detected at bottom transistor xp ? terminal ?0? over current on x h ? bridge; motxp terminal; top tran. ovcxpt 1 status register 1 ?0? = no failure ?1? = failure: indicates that over current is detected at top transistor xp ? terminal ?0? over current on y h ? bridge; motyn terminal; bottom tran. ovcynb 1 status register 2 ?0? = no failure ?1? = failure: indicates that over current is detected at bottom transistor yn ? terminal ?0? over current on y h ? bridge; motyn terminal; top tran. ovcynt 1 status register 2 ?0? = no failure ?1? = failure: indicates that over current is detected at top transistor yn ? terminal ?0? over current on y h ? bridge; motyp terminal; bottom tran. ovcypb 1 status register 2 ?0? = no failure ?1? = failure: indicates that over current is detected at bottom transistor yp ? terminal ?0? over current on y h ? bridge; motyp terminal; top tran. ovcypt 1 status register 2 ?0? = no failure ?1? = failure: indicates that over current is detected at top transistor yp ? terminal ?0? thermal shutdown tsd 1 status register 2 ?0? thermal warning tw 1 status register 0 ?0? watchdog event wd 1 status register 0 ?1? = watchdog reset after time ? out ?0?
amis ? 30512 http://onsemi.com 29 soldering introduction to soldering surface mount packages this text gives a very brief insight to a complex technology. a more in-depth account of soldering ics can be found in the amis ?data handbook ic26; integrated circuit packages? (document order number 9398 652 90011). there is no soldering method that is ideal for all surface mount ic packages. wave soldering is not always suitable for surface mount ics, or for printed-circuit boards (pcb) with high population densities. in these situations re-flow soldering is often used. re ? flow soldering re-flow soldering requires solder paste (a suspension of fine solder particles, flux and binding agent) to be applied to the pcb by screen printing, stencilling or pressure-syringe dispensing before package placement. several methods exist for re-flowing; for example, infrared/convection heating in a conveyor type oven. throughput times (preheating, soldering and cooling) vary between 100 and 200 seconds depending on the heating method. typical re-flow peak temperatures range from 215 to 260 c. the top-surface temperature of the packages should preferably be kept below 230 c. wave soldering conventional single wave soldering is not recommended for surface mount devices (smds) or pcbs with a high component density, as solder bridging and non-wetting can present major problems. to overcome these problems, the double-wave soldering method was specifically developed. if wave soldering is used the following conditions must be observed for optimal results: ? use a double-wave soldering method comprising a turbulent wave with high upward pressure followed by a smooth laminar wave. ? for packages with leads on two sides and a pitch (e): 1. larger than or equal to 1.27 mm, the footprint longitudinal axis is preferred to be parallel to the transport direction of the pcb; 2. smaller than 1.27 mm, the footprint longitudinal axis must be parallel to the transport direction of the pcb. the footprint must incorporate solder thieves at the downstream end. ? for packages with leads on four sides, the footprint must be placed at a 45 angle to the transport direction of the pcb. the footprint must incorporate solder thieves downstream and at the side corners. during placement and before soldering, the package must be fixed with a droplet of adhesive. the adhesive can be applied by screen printing, pin transfer or syringe dispensing. the package can be soldered after the adhesive is cured. typical dwell time is four seconds at 250 c. a mildly-activated flux will eliminate the need for removal of corrosive residues in most applications. manual soldering fix the component by first soldering two diagonally- opposite end leads. use a low voltage (24 v or less) soldering iron applied to the flat part of the lead. contact time must be limited to 10 seconds at up to 300 c. when using a dedicated tool, all other leads can be soldered in one operation within two to five seconds between 270 and 320 c. table 32. soldering process package soldering method wave re-flow (note 7) bga, sqfp not suitable suitable hlqfp, hsqfp, hsop, htssop, sms not suitable (note 8) suitable plcc (note 9) , so, soj suitable suitable lqfp, qfp, tqfp not recommended (notes 9 and 10) suitable ssop, tssop, vso not recommended (note 11) suitable 7. all surface mount (smd) packages are moisture sensitive. depending upon the moisture content, the maximum temperature (with r espect to time) and body size of the package, there is a risk that internal or external package cracks may occur due to vaporization o f the moisture in them (the so called popcorn effect). for details, refer to the drypack information in the ?data handbook ic26; integrated ci rcuit packages; section: packing methods.? 8. these packages are not suitable for wave soldering as a solder joint between the pcb and heatsink (at bottom version) can not be achi eved, and as solder may stick to the heatsink (on top version). 9. if wave soldering is considered, then the package must be placed at a 45 angle to the solder wave direction. the package footprint must incorporate solder thieves downstream and at the side corners. 10. wave soldering is only suitable for lqfp, tqfp and qfp packages with a pitch (e) equal to or larger than 0.8 mm; it is defin itely not suitable for packages with a pitch (e) equal to or smaller than 0.65 mm. 11. wave soldering is only suitable for ssop and tssop packages with a pitch (e) equal to or larger than 0.65 mm; it is definite ly not suitable for packages with a pitch (e) equal to or smaller than 0.5 mm.
amis ? 30512 http://onsemi.com 30 package dimensions 24 lead soic case 751aw issue o on semiconductor and are registered trademarks of semiconductor components industries, llc (scillc). scillc reserves the right to mak e changes without further notice to any products herein. scillc makes no warranty, representation or guarantee regarding the suitability of its products for an y particular purpose, nor does scillc assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including wi thout limitation special, consequential or incidental damages. ?typical? parameters which may be provided in scillc data sheets and/or specifications can and do vary in different application s and actual performance may vary over time. all operating parameters, including ?typicals? must be validated for each customer application by customer?s technical experts. scillc does not convey any license under its patent rights nor the rights of others. scillc products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the scillc product could create a sit uation where personal injury or death may occur. should buyer purchase or use scillc products for any such unintended or unauthorized application, buyer shall indemnify and hold scillc and its of ficers, employees, subsidiaries, af filiates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, direct ly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that scillc was negligent regarding the design or manufacture of the part. scillc is an equal opportunity/affirmative action employer. this literature is subject to all applicable copyright laws and is not for resale in any manner. publication ordering information n. american technical support : 800 ? 282 ? 9855 toll free usa/canada europe, middle east and africa technical support: phone: 421 33 790 2910 japan customer focus center phone: 81 ? 3 ? 5773 ? 3850 amis ? 30512/d literature fulfillment : literature distribution center for on semiconductor p.o. box 5163, denver, colorado 80217 usa phone : 303 ? 675 ? 2175 or 800 ? 344 ? 3860 toll free usa/canada fax : 303 ? 675 ? 2176 or 800 ? 344 ? 3867 toll free usa/canada email : orderlit@onsemi.com on semiconductor website : www.onsemi.com order literature : http://www.onsemi.com/orderlit for additional information, please contact your local sales representative

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